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Exploiting Behavioral Hierarchy for Efficient Model Checking

Inspired by the success of model checking in hardware and protocol verification, model checking techniques for software have been the focus of a lot of research in the last few years [5,3,2,6]. Model checking can be applied only to relatively small models due to its inherently high computational requirements, and there are two complementary trends to address scalability. The model extraction approach, exemplified by projects such as Bandera [6] and SLAM [3], involves constructing inputs to model checkers by abstracting programs written in languages such as C and Java. The model-based design approach, exemplified by modeling notations such as Statecharts [7], promotes design using high-level models that are compiled into code. Our research agenda is to develop model checking techniques for model-based design of software. Modern software design languages promote hierarchy as one of the key constructs for structuring complex specifications. The input language to our model checker is based on hierarchic reactive modules [1]. This choice was motivated by the fact that, unlike STATECHARTS and other languages, in hierarchic reactive modules, the notion of hierarchy is semantic with an observational trace-based semantics and a notion of refinement with assume-guarantee rules. The first contribution of this paper is the Hermes toolkit that implements hierarchic reactive modules. Our implementation has a visual front-end and XML-based back-end, consistent with modern software design tools, and is in Java. There are two basic techniques for reachability analysis. Enumerative model checkers such as SPIN [8] perform an on-the-fly exploration of the state-space using a depth-first search, while symbolic model checkers such as SMV [9] perform a breadth-first search by manipulating sets of states, rather than individual states, encoded typically by ordered binary (or multi-valued) decision diagrams. Since the two approaches are incomparable, and have been shown to be successful, Hermes supports both enumerative and symbolic reachability analysis. In this paper, we report progress on exploiting the structuring information in the behavioral hierarchy of the input model to speed up the exploration of reachable state-space of the model for both the approaches. More information about the tool is available at http://www.cis.upenn.edu/sdrl/hermes

SAT-Based Synthesis Methods for Safety Specs

Automatic synthesis of hardware components from declarative specifications is an ambitious endeavor in computer aided design. Existing synthesis algorithms are often implemented with Binary Decision Diagrams (BDDs), inheriting their scalability limitations. Instead of BDDs, we propose several new methods to synthesize finite-state systems from safety specifications using decision procedures for the satisfiability of quantified and unquantified Boolean formulas (SAT-, QBF- and EPR-solvers). The presented approaches are based on computational learning, templates, or reduction to first-order logic. We also present an efficient parallelization, and optimizations to utilize reachability information and incremental solving. Finally, we compare all methods in an extensive case study. Our new methods outperform BDDs and other existing work on some classes of benchmarks, and our parallelization achieves a super-linear speedup. This is an extended version of [5], featuring an additional appendix.Comment: Extended version of a paper at VMCAI'1

SimpleCAR: An Efficient Bug-Finding Tool Based on Approximate Reachability

We present a new safety hardware model checker SimpleCAR that serves as a reference implementation for evaluating Complementary Approximate Reachability (CAR), a new SAT-based model checking framework inspired by classical reachability analysis. The tool gives a “bottom-line” performance measure for comparing future extensions to the framework. We demonstrate the performance of SimpleCAR on challenging benchmarks from the Hardware Model Checking Competition. Our experiments indicate that SimpleCAR is particularly suited for unsafety checking, or bug-finding; it is able to solve 7 unsafe instances within 1 h that are not solvable by any other state-of-the-art techniques, including BMC and IC3/PDR, within 8 h. We also identify a bug (reports safe instead of unsafe) and 48 counterexample generation errors in the tools compared in our analysis

Intersection and Rotation of Assumption Literals Boosts Bug-Finding

SAT-based techniques comprise the state-of-the-art in functional verification of safety-critical hardware and software, including IC3/PDR-based model checking and Bounded Model Checking (BMC). BMC is the incontrovertible best method for unsafety checking, aka bug-finding. Complementary Approximate Reachability (CAR) and IC3/PDR complement BMC for bug-finding by detecting different sets of bugs. To boost the efficiency of formal verification, we introduce heuristics involving intersection and rotation of the assumption literals used in the SAT encodings of these techniques. The heuristics generate smaller unsat cores and diverse satisfying assignments that help in faster convergence of these techniques, and have negligible runtime overhead. We detail these heuristics, incorporate them in CAR, and perform an extensive experimental evaluation of their performance, showing a 25% boost in bug-finding efficiency of CAR.We contribute a detailed analysis of the effectiveness of these heuristics: their influence on SAT-based bug-finding enables detection of different bugs from BMCbased checking. We find the new heuristics are applicable to IC3/PDR-based algorithms as well, and contribute a modified clause generalization procedure

Uma abordagem para o ensino de produtos notáveis em uma classe inclusiva: o caso de uma aluna com deficiência visual

Acompanha: Produtos notáveisThe research has as its theme the Math teaching and the inclusion of visually challenged students in regular education. This is a research with qualitative approach using a study case as strategy. It aims at the development of didactic-methodological procedures that enable visually challenged included in regular education, as well as other students, to appropriate of mathematical knowledge. This study was based on the socio-historical current for the development of a pedagogical intervention in an 8th grade classroom of a secondary public school in the countryside of Paraná, which had a visually challenged student included. In the intervention were approached concepts of Geometry, Algebra, Values and Measurements such as Area, Perimeter and Volume, with inference of Notable Products. The developed activities were grounded in the Theory of Piotr Yakovlevich Galperin (2009) for the formation of concepts. For the activities development was elaoreted the teaching material “Notable Products” with adaptations for visually challenged students. After the activities implementation it was realized that it is possible to teach Mathematics to visually challenged students with others in a classroom that everyone, regardless of their limitations, are able to elaborate necessary concepts for their autonomy and citizenship practice.Esta pesquisa apresenta como tema o ensino de Matemática e a inclusão de alunos deficientes visuais no ensino regular. Trata-se de uma pesquisa com abordagem qualitativa, utilizando-se do estudo de caso como estratégia. Seu objetivo é o desenvolvimento de procedimentos didático - metodológicos que possibilitem aos deficientes visuais inclusos no ensino regular a apropriação dos conhecimentos matemáticos, assim como os demais alunos. Fundamentou-se nos pressupostos da corrente sócio – histórica para o desenvolvimento de uma intervenção pedagógica em uma turma do oitavo ano do Ensino Fundamental de um colégio público do interior do Paraná, que contava com uma aluna deficiente visual inclusa. Na intervenção foram abordados conceitos matemáticos em Geometria, Álgebra e Grandezas e Medidas como Área, Perímetro e Volume, com inferência aos Produtos Notáveis. As atividades desenvolvidas foram elaboradas fundamentadas na Teoria de Piotr Yakovlevich Galperin (2009) para a formação de conceitos. Para o desenvolvimento das atividades elaborou-se o material didático “Produtos Notáveis”, com adaptações para alunos com deficiência visual. Após a aplicação das atividades, percebeu-se que é possível ensinar Matemática, aos alunos com deficiência visual, juntamente com os demais em uma turma e que todos, independente das limitações, são capazes de elaborar conceitos necessários para a autonomia e o exercício da cidadania

Novel Bypass Attack and BDD-based Tradeoff Analysis Against all Known Logic Locking Attacks

Logic locking has emerged as a promising technique for protecting gate-level semiconductor intellectual property. However, recent work has shown that such gate-level locking techniques are vulnerable to Boolean satisfiability (SAT) attacks. In order to thwart such attacks, several SAT-resistant logic locking techniques have been proposed, which minimize the discriminating ability of input patterns to rule out incorrect keys. In this work, we show that such SAT-resistant logic locking techniques have their own set of unique vulnerabilities. In particular, we propose a novel ``bypass attack that ensures the locked circuit works even when an incorrect key is applied. Such a technique makes it possible for an adversary to be oblivious to the type of SAT-resistant protection applied on the circuit, and still be able to restore the circuit to its correct functionality. We show that such a bypass attack is feasible on a wide range of benchmarks and SAT-resistant techniques, while incurring minimal run-time and area/delay overhead. Binary decision diagrams (BDDs) are utilized to analyze the proposed bypass attack and assess tradeoffs in security vs overhead of various countermeasures